Skip to main content

Circuit-Level Secure-by-Design Field Programmable Gate Arrays

Researcher: Ken Mai

Research Area: Next Generation Secure and Available Networks

Cross Cutting Thrusts: Software Security

Abstract

The long development time and high non-recurring engineering costs associated with modern integrated circuit design have pushed many system designers to use field programmable gate arrays (FPGAs) in lieu of custom ASICs as FPGAs offer much of the flexibility of software programmed CPUs, but still achieve much of the performance and efficiency of custom ASICs. However commercial off-the-shelf (COTS) FPGAs lack a number features necessary in secure systems such as counter-tamper technology, secure operation, and secure manufacturing. We are implementing a circuit-level secure-by-design FPGA by employing novel circuit and micro-architectural techniques and by leveraging the reconfigurable nature of FPGAs to enhance the security beyond even that of secure custom ASICs.

Specifically, we are securing designs at the hardware level by developing techniques for: efficient side-channel-secure logic circuits; remanence-free semiconductor memory circuits; self-monitoring of power consumption, delay, and logical correctness to detect probing, fault injection, side-channel leakage, and maliciously inserted circuits; and self-reconfiguration to reduce side-channel leakage and to hinder fault-injection and probing. By implementing hardware security features in the FPGA itself (rather than addressing security at the tool/application-level), the FPGA can be hardened in a virtually user-transparent manner, minimally disrupting the user-level RTL application design and FPGA programming/compilation tool flow. The secure FPGA prototype chip would be the first-reported FPGA designed specifically for secure operation and serve as a clear proof-of-concept for the proposed techniques.