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Ken Mai

Senior Systems Scientist, Electrical and Computer Engineering

[Email]

Ken Mai

Research Areas

Mobility, Next Generation Secure and Available Networks, Secure Home Computing, Trustworthy Computing Platforms and Devices

Cross Cutting Thrusts

Cryptography, Software Security

Biography

Ken Mai is a Senior Systems Scientist in Electrical and Computer Engineering.

His research interests are with process technologies scaling into the nanometer regime, the underlying implementation technology increasingly affects architecture and circuit design. We must adapt and reinvent current designs to circumvent technology constraints (e.g. interconnect delay, device leakage, soft-errors, device mismatch) and to target emerging applications (e.g. sensor networks, computational biology). The key near-term challenge is to build computer systems that can efficiently achieve high-performance, yet remain economically feasible, general-purpose, and easy to program. In the long-term, with CMOS scaling approaching fundamental limits, the challenge will be to build efficient, high-performance, reliable computation systems from technology building blocks that may be radically different from those we use today.

His primary research interest is the circuit design of efficient, high-performance digital blocks (i.e. memories and functional units) in future generation technologies. Further,his interests lie in building tools to export VLSI-level design information and constraints to architectural-level design.

Education

PhD, 2005. Electrical Engineering, Stanford University
MS, 1997. Electrical Engineering, Stanford University
BS, 1993. Electrical Engineering, Stanford University

Research Projects

Efficiently Securing Non-Volatile Storage in Portable Systems

Research Area: Mobility | Trustworthy Computing Platforms and Devices | Secure Home Computing
Researcher: Ken Mai

Secure, Reliable, Efficient Physical Unclonable Functions

Research Area: Trustworthy Computing Platforms and Devices
Cross Cutting Thrusts: Cryptography
Researcher: Ken Mai

Efficient, Secure Encryption Implementations

Research Area: Trustworthy Computing Platforms and Devices
Cross Cutting Thrusts: Cryptography
Researcher: Ken Mai

Inherently Trojan-Resistant Integrated Circuit Architectures

Research Area: Trustworthy Computing Platforms and Devices
Cross Cutting Thrusts: Cryptography
Researcher: Ken Mai

Circuit-Level Secure-by-Design Digital Integrated Circuits

Research Area: Trustworthy Computing Platforms and Devices
Researcher: Ken Mai

Circuit-Level Secure-by-Design Field Programmable Gate Arrays

Research Area: Next Generation Secure and Available Networks
Cross Cutting Thrusts: Software Security
Researcher: Ken Mai

Publications

"Data Retention in MLC NAND Flash Memory: Characterization, Optimization and Recovery; nominated for best paper award," Y. Cai, Y. Luo, E. F. Haratsch, K. W. Mai, and O. Mutlu, HPCA: IEEE International Symposium on High-Performance Compute Architecture, 2015.

"Comparative Evaluation of FPGA and ASIC Implementations of Bufferless and Buffered Routing Algorithms for On-Chip Networks," Y. Cai, K. W. Mai, and O. Mutlu, ISQED: International Symposium on Quality Electronic Design, 2015.

"SLIC: Statistical Learning in Chip," R. D. Blanton, X. Li, K. W. Mai, D. Marculescu, R. Marculescu, J. Paramesh, J. Schneider, and D. E. Thomas,  ISIC: International Symposium on Integrated Circuits, 2014.

"Neighbor-Cell Assisted Error Correction for MLC NAND Flash Memories," Y. Cai, G. Yalcin, O. Mutlu, E. Haratsch, O. Unsal, A. Cristal, and K. W. Mai,  ACM Sigmetrics Conference, pp. 491-504, 2014.

"An Efficient Reliable PUF-Based Cryptographic Key Generator in 65nm CMOS". Bhargava, M., & Mai, K. W. (2014). Design, Automation, and Test in Europe Conference (DATE).

"Building Fast, Dense, Low-Power Caches Using Erasure-Based Inline Multi-Bit ECC". Kim, J., McCartney, M., Bhargava, M., Yang, H., Mai, K. W., & Falsafi, B. (2013). Pacific Rim International Symposium on Dependable Computing (PRDC).

"Error Analysis and Retention-Aware Error Management for NAND Flash Memory". Cai, Y., Yalcin, G., Mutlu, O., Haratsch, E., Cristal, A., Unsal, O., & Mai, K. W. (2013). Intel Technology Journal, 17(1), 140-164.

" SCAN-PUF: A Low Overhead Physically Unclonable Function from Scan Chain Power-Up States". Niewenhuis, B., Blanton, R. D., Bhargava, M., & Mai, K. W. (2013). International Test Conference, 1-8.

"Threshold Voltage Distribution in MLC NAND Flash Memory: Characterization, Analysis, and Modeling". Cai, Y., Haratsch, E., Mutlu, O., & Mai, K. W. (2013). DATE: Design Automation and Test in Europe, 1285-1290.